1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having an ECC circuit.
2. Description of the Related Art
The storage node capacity of each of the cells which configure a memory is reduced by the miniaturization of elements concurrent with the development of semiconductor device technology, and therefore, soft errors of the memory develop into a serious problem. As a countermeasure against soft errors, an ECC circuit (Error Correcting Code) circuit is often mounted on a memory section in the chip. A memory having an ECC circuit mounted thereon stores checking code bits in addition to normal data bits, detects the presence or absence of an error in the data bits based on the value of the code bit and one of the bits in which the error occurs by use of the ECC circuit, corrects the error and outputs the error-corrected bit to the exterior. The number of error bits in the same word which the ECC can correct is determined according to a code used. Generally, a SEC-DED (Single Error Correction-Double Error Detection) code which can be used for 1-bit error correction or for two-bit error detection in addition to 1-bit error correction is widely used.
FIG. 11 shows the configuration of a typical semiconductor memory with an ECC circuit. The number of code bits required for correcting a 1-bit error varies according to the number of data bits. For example, in order to correct a 1-bit error in 32-bit data as shown in FIG. 11, a 7-bit code is required. Therefore, a total memory capacity which is 1.22 times the original memory capacity is required.
In order to suppress an increase in the memory capacity due to the code bits, a method for applying the ECC circuit to deal with data bits of a larger number in the memory is provided. For example, as shown in FIG. 12, an ECC circuit is used to deal with internal 128-bit data, select desired 32-bit data from the corrected 128 bit data and output the selected data. In this case, since a code of nine bits may be used for 128-bit data, the total memory capacity can be suppressed to 1.07 times the original memory capacity.
An example of a semiconductor memory to which the above ECC circuit is applied is described in document 1.
Document 1: Kazutami Arimoto et al., “A Speed-Enhanced DRAM Array Architecture with Embedded ECC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 1, February 1990, pp. 11–17.